![]() Wa_emtcontenttype: "emtcontenttype:datasheetsspecificationsandschematics/productspecification/deviceoverviews", Same as Standard PCS plus GigE state machine Same as Standard PCS plus deterministic latency deserializationįIFO, channel bonding, bit-slipper, and gear boxįIFO, block sync, bit-slipper, and gear boxįIFO, 64B/66B encoder, scrambler, FEC, and gear boxįIFO, 64B/66B decoder, descrambler, block sync, FEC, and gear boxįIFO, channel bonding, frame generator, CRC-32 generator, scrambler, disparity generator, bit-slipper, and gear boxįIFO, CRC-32 checker, frame sync, descrambler, disparity checker, block sync, and gear boxįIFO (fixed latency), 64B/66B encoder, scrambler, and gear boxįIFO (fixed latency), 64B/66B decoder, descrambler, block sync, and gear box Same as Standard PCS plus deterministic latency serialization Rate match FIFO (0-600 ppm mode), word-aligner, decoder, descrambler, phase compensation FIFO, block sync, byte deserializer, byte ordering, PIPE 3.0 interface to core, auto speed negotiation Phase compensation FIFO, byte serializer, encoder, scrambler, bit-slipper, gear box, channel bonding, and PIPE 3.0 interface to core, auto speed negotiation Same as Standard PCS plus PIPE 2.0 interface to core PCI Express Gen1/Gen2 x1, x2, x4, x8, x16 Rate match FIFO, word-aligner, 8B/10B decoder, byte deserializer, byte ordering Phase compensation FIFO, byte serializer, 8B/10B encoder, bit-slipper, channel bonding For highly customized implementations, a PCS Direct mode provides an interface up to 64 bits wide to allow for custom encoding and support for data rates up to 28.9 Gbps.įor more information about the PCS-Core interface or the double rate transfer mode, refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide, and the Intel® Stratix® 10 E-Tile Transceiver PHY User Guide. The enhanced PCS mode also includes an integrated 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) circuit. The Enhanced PCS mode supports 64B/66B and 64B/67B encoded applications up to 17.4 Gbps. The Standard PCS mode provides support for 8B/10B encoded applications up to 12.5 Gbps. The PCS also contains hard IP to support a variety of standard and proprietary protocols across a wide range of data rates and encoding schemes. This feature provides the flexibility to implement a wide range of applications with 8, 10, 16, 20, 32, 40, or 64 bit interface width between each transceiver and the core logic. The PCS contains multiple gearbox implementations to decouple the PMA and PCS interface widths. Intel® Stratix® 10 MX PMA channels interface with core logic through configurable and bypassable PCS interface layers. Document Revision History for the Intel® Stratix® 10 MX (DRAM System-in-Package) Device Overview Single Event Upset (SEU) Error Detection and Correction 1.27. Partial and Dynamic Reconfiguration 1.25. Configuration via Protocol Using PCI Express* 1.24. Device Configuration and Secure Device Manager (SDM) 1.22. Fractional Synthesis PLLs and I/O PLLs 1.18. External Memory and General Purpose I/O 1.15. 100G Ethernet MAC, Reed-Solomon FEC Hard IP, and KP-FEC Hard IP 1.12. Heterogeneous 3D SiP Transceiver Tiles 1.9. Heterogeneous 3D Stacked HBM2 DRAM Memory 1.7. ![]() Intel® Stratix® 10 MX Features Summary 1.4. Innovations in Intel® Stratix® 10 MX Devices 1.3.
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